Description of the Prior Art
Bucket brigade shift registers which operate based on the concept of transfer of charge deficit from stage to stage have been taught in an article by F. L. J. Sangster, entitled "The Bucket Brigade Delay Line: A Shift Register for Analogue Signals", which appeared on pages 92-110 of Volume 31, No. 4, 1970, of the Phillips Technical Review.
Broadly the bucket brigade concept taught by Sangster uses as each stage for the register a transistor and a capacitor and operates by causing the present charge on a first stage to be shifted from the capacitor in the first stage to the capacitor in the next adjacent stage.
Generally, a two phase shift register employs two, non-overlapping clock pulses 01 and 02. In such a shift register, only one-half of the storage capacitors of the array contain a signal sample at any given time.
FIG. 1 is a symbolic illustration of a transversal filter comprised of a sequence of delay blocks (D) fed by a signal input sampler block (S), with the nodes between the delay blocks (D) being respectively connected to tap weighting means H.sub.1 through H.sub.M, the output of which are summed as an output signal. In operation, the transversal filter receives an input signal V(t) having a first waveform, which is sequentially delayed by the delay blocks D so that sampled delayed replicas of V(t), V.sub.1 through V.sub.M, are respectively multiplied by tap weights H.sub.1 through H.sub.M, and the weighted products are summed to generate an output signal. The total transfer function may be programmed by programming the values of the tap weights.
FIG. 2 shows a conventional bucket brigade device, which operates as a connected sequence of delay stages. FIG. 3 describes a voltage divider technique employing precision resistors to form weighted taps at the nodes of successive FET device pairs in the bucket brigade circuit. In operation, the node between the drain of T1 and, the source of T2 in the circuit of FIG. 3, has a charge stored on the capacitor thereof, the magnitude of which is the analog signal to be weighted. The voltage corresponding to that charge is applied to the gate of transistor Q1 whose drain is connected to a positive power supply and whose source is connected to a precision resistor voltage divider, R1a-R1b. The magnitude of the charge at the node between T1 and T2 governs the conductivity of the transistor Q1 and thus the signal amplitude at the output 01 at the drain of transistor Q1. A significant problem which characterizes this approach to weighted taps is that the precision of the resistors R1 through RN cannot be held to close tolerances with diffused resistors in an integrated circuit structure. The poor performance of this prior voltage divider circuit precludes its use in integrated circuit implementations.
U.S. Pat. No. 3,809,923 to Esser discloses a transversal filter having adjustable weighting factors for a bucket brigade storage shift register. The goal of the patent is charge partitioning but the method for accomplishing it requires the availability of analog weighting signals, Column 4, line 43. Thus, the precision of the tap weighting in Esser is a function of the precision of the analog weighting signals, the tolerance of which is a function not only of the power supply tolerance, but also the tolerances of a variety of semiconductor device parameters.